| Optimal detector for multilevel NAND flash memory channels with intercell interference M Asadi, X Huang, A Kavcic, NP Santhanam IEEE Journal on Selected Areas in Communications 32 (5), 825-835, 2014 | 43 | 2014 |
| Deep learning based regression framework for read thresholds in a NAND flash memory C Xiong, F Zhang, X Lu, M Asadi, J Chen US Patent 10,861,562, 2020 | 18 | 2020 |
| Stationary and transition probabilities in slow mixing, long memory markov processes M Asadi, RP Torghabeh, NP Santhanam IEEE Transactions on Information Theory 60 (9), 5682-5701, 2014 | 18 | 2014 |
| Recurrent wavelet network with new initialization and its application on short-term load forecasting A Baniamerian, M Asadi, E Yavari 2009 Third UKSim European Symposium on Computer Modeling and Simulation, 379-383, 2009 | 11 | 2009 |
| Error mitigation scheme for bit-flipping decoders for irregular low-density parity-check codes C Xiong, F Zhang, H Wang, X Lu, M Asadi US Patent 11,184,024, 2021 | 9 | 2021 |
| On the zero-error capacity of channels with noisy feedback M Asadi, N Devroye 2017 55th Annual Allerton Conference on Communication, Control, and …, 2017 | 8 | 2017 |
| Decoding codeword based on higher order information M Asadi, F Zhang, A Bhatia US Patent 11,381,253, 2022 | 6 | 2022 |
| Performance of a bit flipping (BF) decoder of an error correction system X Lu, F Zhang, A Bhatia, M Asadi, H Wang US Patent 11,108,407, 2021 | 6 | 2021 |
| All-bit-line MLC flash memories: Optimal detection strategies X Huang, M Asadi, A Kavcic, NP Santhanam 2014 IEEE International Conference on Communications (ICC), 3883-3888, 2014 | 6 | 2014 |
| Estimation in slow mixing, long memory channels M Asadi, RP Torghabeh, NP Santhanam 2013 IEEE International Symposium on Information Theory, 2104-2108, 2013 | 6 | 2013 |
| Fast fail support for error correction in non-volatile memory F Zhang, C Xiong, X Lu, M Asadi US Patent 11,139,831, 2021 | 4 | 2021 |
| Read retry threshold voltage selection X Lu, F Zhang, C Xiong, H Wang, M Asadi US Patent 11,127,471, 2021 | 4 | 2021 |
| Dynamic control of quasi-cyclic low-density parity-check bit-flipping decoder M Asadi, A Bhatia, F Zhang, H Wang US Patent 11,190,212, 2021 | 3 | 2021 |
| Fast-converging soft bit-flipping decoder for low-density parity-check codes M Asadi, F Zhang, H Wang, H Duan US Patent 11,043,969, 2021 | 3 | 2021 |
| Error exponents of parallel two-way discrete memoryless channels using variable length coding K Palacio-Baus, M Asadi, N Devroye 2019 IEEE International Symposium on Information Theory (ISIT), 2249-2253, 2019 | 3 | 2019 |
| A relaying graph and special strong product for zero-error problems in primitive relay channels M Asadi, K Palacio-Baus, N Devroye 2018 IEEE International Symposium on Information Theory (ISIT), 281-285, 2018 | 3 | 2018 |
| A modified BCE algorithm for fault-tolerance scheduling of periodic tasks in hard real-time systems M Asadi, MB Menhaj, E Yavari 2009 Third Asia International Conference on Modelling & Simulation, 287-291, 2009 | 3 | 2009 |
| Read threshold optimization systems and methods using domain transformation F Zhang, A Bhatia, H Wang US Patent 11,907,571, 2024 | 2 | 2024 |
| Capacitance coupling parameter estimation in flash memories M Asadi, Z Chen, EF Haratsch US Patent 11,430,529, 2022 | 2 | 2022 |
| Bit-flipping decoder architecture for irregular quasi-cyclic low-density parity-check codes M Asadi, F Zhang, A Bhatia, X Lu, H Wang US Patent 11,206,043, 2021 | 2 | 2021 |
Narayana SanthanamUniversity of HawaiiVerified email at hawaii.edu
