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Meysam Asadi
Meysam Asadi
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Cited by
Year
Optimal detector for multilevel NAND flash memory channels with intercell interference
M Asadi, X Huang, A Kavcic, NP Santhanam
IEEE Journal on Selected Areas in Communications 32 (5), 825-835, 2014
422014
Stationary and transition probabilities in slow mixing, long memory markov processes
M Asadi, RP Torghabeh, NP Santhanam
IEEE Transactions on Information Theory 60 (9), 5682-5701, 2014
172014
Deep learning based regression framework for read thresholds in a NAND flash memory
C Xiong, F Zhang, X Lu, M Asadi, J Chen
US Patent 10,861,562, 2020
152020
Recurrent wavelet network with new initialization and its application on short-term load forecasting
A Baniamerian, M Asadi, E Yavari
2009 Third UKSim European Symposium on Computer Modeling and Simulation, 379-383, 2009
112009
On the zero-error capacity of channels with noisy feedback
M Asadi, N Devroye
2017 55th Annual Allerton Conference on Communication, Control, and …, 2017
82017
All-bit-line MLC flash memories: Optimal detection strategies
X Huang, M Asadi, A Kavcic, NP Santhanam
2014 IEEE International Conference on Communications (ICC), 3883-3888, 2014
62014
Estimation in slow mixing, long memory channels
M Asadi, RP Torghabeh, NP Santhanam
2013 IEEE International Symposium on Information Theory, 2104-2108, 2013
62013
Decoding codeword based on higher order information
M Asadi, F Zhang, A Bhatia
US Patent 11,381,253, 2022
42022
Read retry threshold voltage selection
X Lu, F Zhang, C Xiong, H Wang, M Asadi
US Patent 11,127,471, 2021
42021
Performance of a bit flipping (BF) decoder of an error correction system
X Lu, F Zhang, A Bhatia, M Asadi, H Wang
US Patent 11,108,407, 2021
42021
Fast-converging soft bit-flipping decoder for low-density parity-check codes
M Asadi, F Zhang, H Wang, H Duan
US Patent 11,043,969, 2021
32021
Error exponents of parallel two-way discrete memoryless channels using variable length coding
K Palacio-Baus, M Asadi, N Devroye
2019 IEEE International Symposium on Information Theory (ISIT), 2249-2253, 2019
32019
A relaying graph and special strong product for zero-error problems in primitive relay channels
M Asadi, K Palacio-Baus, N Devroye
2018 IEEE International Symposium on Information Theory (ISIT), 281-285, 2018
32018
A modified BCE algorithm for fault-tolerance scheduling of periodic tasks in hard real-time systems
M Asadi, MB Menhaj, E Yavari
2009 Third Asia International Conference on Modelling & Simulation, 287-291, 2009
32009
Capacitance coupling parameter estimation in flash memories
M Asadi, Z Chen, EF Haratsch
US Patent 11,430,529, 2022
22022
Read threshold optimization systems and methods using domain transformation
F Zhang, A Bhatia, X Lu, M Asadi, H Wang
US Patent App. 16/927,567, 2022
22022
Error mitigation scheme for bit-flipping decoders for irregular low-density parity-check codes
C Xiong, F Zhang, H Wang, X Lu, M Asadi
US Patent 11,184,024, 2021
22021
Error characteristic estimation for NAND flash
F Zhang, C Xiong, M Asadi, X Lu
US Patent 11,128,314, 2021
22021
Capacitance coupling parameter estimation in flash memories
M Asadi, Z Chen, EF Haratsch
US Patent 9,934,867, 2018
22018
Memory channel detector systems and methods
M Asadi, X Huang, A Kavcic
US Patent 9,355,716, 2016
22016
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