| An event-driven multithreaded dynamic optimization framework W Zhang, B Calder, DM Tullsen 14th International Conference on Parallel Architectures and Compilation …, 2005 | 87 | 2005 |
| Accelerating and adapting precomputation threads for effcient prefetching W Zhang, DM Tullsen, B Calder 2007 IEEE 13th International Symposium on High Performance Computer …, 2007 | 84 | 2007 |
| iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture P Gu, X Xie, Y Ding, G Chen, W Zhang, D Niu, Y Xie ISCA-2020, 2020 | 78 | 2020 |
| A self-repairing prefetcher in an event-driven dynamic optimization framework W Zhang, B Calder, DM Tullsen International Symposium on Code Generation and Optimization (CGO'06), 12 pp.-64, 2006 | 46 | 2006 |
| Software-defined design space exploration for an efficient DNN accelerator architecture Y Yu, Y Li, S Che, NK Jha, W Zhang IEEE Transactions on Computers 70 (1), 45-56, 2020 | 30 | 2020 |
| EGEMM-TC: Accelerating Scientific Computing on Tensor Cores with Extended Precision B Feng, Y Wang, G Chen, W Zhang, Y Xie, Y Ding Principles and Practice of Parallel Programming (PPoPP-21), 2021 | 29 | 2021 |
| Regularized Training and Tight Certification for Randomized Smoothed Classifier with Provable Robustness H Feng, C Wu, G Chen, W Zhang, Y Ning Thirsty-Fourth AAAI Conference On Artificial Intelligence, 2020 | 13 | 2020 |
| N3h-core: Neuron-designed neural network accelerator via fpga-based heterogeneous computing cores Y Gong, Z Xu, Z He, W Zhang, X Tu, X Liang, L Jiang Proceedings of the 2022 ACM/SIGDA International Symposium on Field …, 2022 | 12 | 2022 |
| Hardware-guided symbiotic training for compact, accurate, yet execution-efficient LSTM H Yin, G Chen, Y Li, S Che, W Zhang, NK Jha arXiv preprint arXiv:1901.10997, 2019 | 12 | 2019 |
| Enabling Energy-Efficient DNN Training on Hybrid GPU-FPGA Accelerators X He, J Liu, Z Xie, H Chen, G Chen, W Zhang, D Li International Conference on Supercomputing 2021 (ICS-21), 2021 | 10 | 2021 |
| Dynamic code value specialization using the trace cache fill unit W Zhang, S Checkoway, B Calder, DM Tullsen 2006 International Conference on Computer Design, 10-16, 2006 | 8 | 2006 |
| Data layout optimization on processing in memory architecture for executing neural network model Z Minxuan, C Guoyang, W Zhang US Patent 11,669,443, 2023 | 6 | 2023 |
| Parallel training via computation graph transformation F Wang, G Chen, W Zhang, T Rompf 2019 IEEE International Conference on Big Data (Big Data), 3430-3439, 2019 | 6 | 2019 |
| SIMPLE AUGMENTATION GOES A LONG WAY: ADRL FOR DNN QUANTIZATION L Ning, G Chen, W Zhang, X Shen The Ninth International Conference on Learning Representations (ICLR-2021), 2021 | 5 | 2021 |
| Sionnx: Automatic unit test generator for onnx conformance X Cai, P Zhou, S Ding, G Chen, W Zhang arXiv preprint arXiv:1906.05676, 2019 | 5 | 2019 |
| PIM-DL: Boosting DNN Inference on Digital Processing In-Memory Architectures via Data Layout Optimizations M Zhou, G Chen, M Imani, S Gupta, W Zhang, T Rosing The 30th International Conference on Parallel Architectures and Compilation …, 2021 | 3 | 2021 |
| Detecting error in executing computation graph on heterogeneous computing devices W Zhang US Patent 11,113,140, 2021 | 3 | 2021 |
| Method and device for matrix multiplication optimization using vector registers C Guoyang, Y Pu, Y Zhang, W Zhang, Y Xie US Patent 11,366,875, 2022 | 1 | 2022 |
| System and method for allocating memory space S Li, D Niu, F Sun, CHU Jingjun, H Zheng, C Guoyang, Y Li, W Zhang, ... US Patent 11,263,131, 2022 | 1 | 2022 |
| Energy-efficient and quality-assured approximate computing framework using a co-training method L Jiang, Z Song, H Song, C Xu, Q Xu, N Jing, W Zhang, X Liang ACM Transactions on Design Automation of Electronic Systems (TODAES) 24 (6 …, 2019 | 1 | 2019 |
Brad CalderGoogleDirección de correo verificada de google.com
