| High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory and slower-speed memory S Iyer, N McKeown US Patent 7,657,706, 2010 | 389 | 2010 |
| An approach to alleviate link overload as observed on an IP backbone S Iyer, S Bhattacharyya, N Taft, C Diot IEEE INFOCOM 2003. Twenty-second Annual Joint Conference of the IEEE …, 2003 | 198 | 2003 |
| Practical algorithms for performance guarantees in buffered crossbars ST Chuang, S Iyer, N McKeown Proceedings IEEE 24th Annual Joint Conference of the IEEE Computer and …, 2005 | 177 | 2005 |
| Making parallel packet switches practical S Iyer, N McKeown Proceedings IEEE INFOCOM 2001. Conference on Computer Communications …, 2001 | 166 | 2001 |
| Analysis of a packet switch with memories running slower than the line-rate S Iyer, A Awadallah, N McKeown Proceedings IEEE INFOCOM 2000. Conference on Computer Communications …, 2000 | 166 | 2000 |
| Analysis of the parallel packet switch architecture S Iyer, NW McKeown IEEE/ACM Transactions on Networking 11 (2), 314-324, 2003 | 165 | 2003 |
| Designing packet buffers for router linecards S Iyer, RR Kompella, N McKeown IEEE/ACM Transactions On Networking 16 (3), 705-717, 2008 | 162 | 2008 |
| Control system for high speed rule processors V Chopra, A Desai, R Iyer, S Iyer, M Jiandani, A Shelat, N Yadav US Patent 6,611,875, 2003 | 153 | 2003 |
| Routers with a single stage of buffering S Iyer, R Zhang, N McKeown Proceedings of the 2002 conference on Applications, technologies …, 2002 | 124 | 2002 |
| Analysis of a memory architecture for fast packet buffers S Iyer, RR Kompella, N McKeowa 2001 IEEE Workshop on High Performance Switching and Routing (IEEE Cat. No …, 2001 | 123 | 2001 |
| Method and apparatus for high-speed network rule processing S Bal, R Iyer, S Iyer, R Rao US Patent 6,691,168, 2004 | 119 | 2004 |
| Method and apparatus for high-speed network rule processing V Chopra, A Desai, R Iyer, S Iyer, M Jiandani, A Shelat, N Yadav US Patent 6,510,509, 2003 | 116 | 2003 |
| Maintaining statistics counters in router line cards D Shah, S Iyer, B Prahhakar, N McKeown IEEE Micro 22 (1), 76-81, 2002 | 110 | 2002 |
| Intelligent memory system compiler S Iyer, S Joshi, ST Chuang US Patent 8,589,851, 2013 | 101 | 2013 |
| Method and apparatus for performing internet network address translation S Bal, R Iyer, S Iyer US Patent 6,457,061, 2002 | 93 | 2002 |
| Fast, deterministic exact match look-ups in large tables D Joshi, A Shelat, A Phansalkar, S Iyer, R Kompella, G Varghese US Patent 7,043,494, 2006 | 88 | 2006 |
| ClassiPl: an architecture for fast and flexible packet classification S Iyer, RR Kompella, A Shelat IEEE Network 15 (2), 33-41, 2001 | 75 | 2001 |
| High speed memory systems and methods for designing hierarchical memory systems S Iyer, ST Chuang US Patent 9,442,846, 2016 | 57* | 2016 |
| Method for deflection routing of data packets to alleviate link overload in IP networks N Taft, S Bhattacharyya, C Diot, S Iyer US Patent 7,362,703, 2008 | 57 | 2008 |
| Analysis of a statistics counter architecture D Shah, S Iyer, B Prabhakar, N McKeown HOT 9 Interconnects. Symposium on High Performance Interconnects, 107-111, 2001 | 48 | 2001 |
Nick McKeownStanford UniversityDirección de correo verificada de stanford.edu
